Features

Everything RyuSim v1 offers for RTL simulation.

4-State Logic

Full 0, 1, X, Z value simulation with correct propagation semantics.

Synthesizable SV Subset

IEEE 1800-2023 always_comb, always_ff, always_latch, generate for/if, interfaces, packages, parameters.

VPI-First Design

V1 is a VPI-only simulator. Write testbenches in Python using cocotb with full signal read/write access.

Event-Driven Kernel

Correct scheduling semantics with proper delta cycles and event ordering.

Code Coverage

Line, branch, and toggle coverage with LCOV output. Coverage merge across test runs. Early

Waveform Generation

VCD and FST format output for waveform viewing in GTKWave or other viewers. Early

SystemVerilog Feature Support

Category Feature Status
Process Blocks always_comb ✅
Process Blocks always_ff ✅
Process Blocks always_latch ✅
Data Types logic, wire, reg ✅
Data Types packed arrays ✅
Data Types enums ✅
Data Types structs (packed) ✅
Hierarchy module instantiation ✅
Hierarchy generate for/if ✅
Hierarchy interfaces ✅
Hierarchy packages ✅
Operators arithmetic, logical, bitwise ✅
Operators shift (<<, >>, >>>, <<<) ✅
Operators concatenation, replication ✅
Operators ternary (?:) ✅
Control Flow if/else, case/casez/casex ✅
Control Flow for loops (synthesizable) ✅
Parameters parameter, localparam ✅
Parameters parameter override ✅
Assignments continuous assign ✅
Assignments blocking / non-blocking ✅

RyuSim v1 is a VPI-only simulator. All testbench stimulus and verification is done through the VPI interface, primarily using cocotb. Non-synthesizable SystemVerilog constructs (delays, fork/join, classes) are not supported.